1. Field of the Invention
This invention relates to generating control signals, and more particularly to a system and method for controlling the operation of an oscillation circuit such as a phase-locked loop.
2. Description of the Related Art
Phase-locked loop (PLL) circuits are desirable because of their ability to produce a stable output frequency. They are commonly used, for example, to generate mixing signals in communications systems, clock signals for controlling the speed and synchronizing the operation of microprocessor systems, and timing signals for transferring data in various data storage applications.
Next-generation communications systems and processing architectures will inevitably run at faster speeds than are currently attainable. This will require a commensurate increase in the frequency of their driving clock signals. At very high frequencies, a type of phase error known as jitter has a more severe affect on system performance. Even at current frequencies, however, jitter will have a major adverse effect on the operating frequency of microprocessor systems as well as the bit-error rate. It is further noted that the negative jitter effect is higher at higher frequencies.
A principal source of jitter in a phase-locked loop circuit is leakage current in sensitive nodes, like the steering node of a voltage-controlled oscillator. In conventional self-biased phase-locked loops, transistors including those in startup circuits are a major contributor to this effect. Conventional startup circuits are also slow (taking anywhere from 0.5 to 1.5 μs to respond) which further impairs the performance of the self-biased PLL.
Recently, efforts have been made to improve PLL performance by increasing the speed of the startup circuit. Designers have discovered, however, that a significant tradeoff exists between the speed of the startup circuit and leakage. For example, conventional approaches attempt to increase the speed of PLL startup circuits by using larger transistors. Unfortunately, larger transistors produce greater leakage, which results in a proportional increase in the amount of jitter in the self-biased PLL.